// 四分频
module div_clk(
    input clk,
    input rst,
    output reg clkd
);
    reg cnt;
    always @(posedge clk or posedge rst) begin
        if(rst)
            cnt<=0;
        else
            cnt<=cnt+1;
    end
    always @(posedge clk or posedge rst) begin
        if(rst)
            clkd<=0;
        else if(cnt)
            clkd<=~clkd;
    end
endmodule

